The memory space of a computer is often composed of random access memories (RAMs) residing on RAM cards which are connected to the data and address busses of the computer. The RAMs, which may be of different sizes such as 64K and 256K, each have a predetermined address within the memory space and each individual RAM memory location has a specific address within the RAM. In practice, the upper bits of a memory address specify a particular RAM and the lower bits specify a given memory location within that RAM.
In computers which are constructed according to the prior art it is known to specify the location of a RAM within the memory space by physically setting an address on a switch array. A given RAM is enabled when a comparator on the RAM card indicates that an address on the bus is the same as the RAM address on the switch array. In such prior art computers it is necessary for the user to set the specified address of each RAM on the RAM card switch array. The use of such switches introduces the possibility of user error and user-caused damage to the computer.
In accordance with the illustrated preferred embodiment of the present invention, the RAMs comprising the 32 bit wide memory space of a computer are automatically located within the memory space and address enable information is stored in ID-RAMs on each RAM card. The RAM cards are physically placed in the computer back plane so that the RAMs are located within the memory space in a descending order by size. Each RAM card includes three RAMs, a data buffer, an ID-RAM and a three cell shift register. Each shift register cell is capable of storing a single bit. The shift registers of the various RAM cards are connected in series and during initialization an ID "1" bit is clocked through the shift registers. A detector detects a transfer of the ID bit between two adjacent RAM cards so that the memory boundaries of each RAM card, and the size of the RAMs on each RAM card, may be determined. At each clock pulse the three bit contents of each shift register are written to the ID-RAM for that shift register. Thus, only twelve memory locations within each ID-RAM of a 256K RAM card, and three memory locations within the ID-RAM of a 64K RAM card, contain an ID bit and the addresses of those ID-RAM memory locations comprise the upper bits of the addresses of the RAMs on the RAM cards. The location of the ID bit within the three bit memory location ndicates which of the three RAMs on a RAM card is thereby accessed. The lower bits of the address specify individual memory locations within each RAM.